Cadence Presents Multi-Protocol DDR4 and LPDDR4 IP Solution

Cadence Design Systems, Inc., a global electronic design innovation provider, has announced the multi-protocol DDR4 and LPDDR4 intellectual property (IP) Solution. The Cadence® DDR controller and PHY IP can scale up to 3200Mbps, which provides flexibility for designers to easily take advantage of higher performance DDR4 and LPDDR4 DRAMs when they become available, without having to redesign their systems on chip (SoCs).

With a single, multi-protocol IP, designers can easily address changing memory and system cost requirements in consumer, mobile and enterprise applications. They can select the optimal DRAM subsystem implementation for their specific application after the SoC has already been designed.

DDR4 is primarily used in enterprise applications requiring high-capacity and high-reliability DRAM subsystems. LPDDR4 meets the power/performance requirements of mobile applications. Consumer applications, on the other hand, have traditionally used DDR3 DRAMs, moving to DDR4 to benefit from DRAM commodity pricing. Over time, performance requirements for these application areas are currently expected to grow, while performance levels for LPDDR4 are expected to improve. With the new IP, designers can easily migrate from DDR4 to LPDDR4 without a chip redesign.

“The Cadence DDR PHY IP offers high performance, high configurability and flexibility critical to our networking SoC designs,” said Gaurav Singh, vice president technical strategy at Applied Micro Circuits Corporation. “With access to the next-generation protocol and having additional flexibility between DDR and LPDDR, Cadence is allowing us to further innovate and provide greater differentiation and value to our customers.”

“For the first time, high performance mobile, consumer and enterprise application requirements can be addressed in a single DDR IP solution,” said Martin Lund, senior vice president of the IP Group at Cadence. “By using the Cadence multi-protocol DDR IP, we believe our customers can have more confidence that their products can meet memory subsystem requirements, allowing them to optimize for performance, power and density in their end system.”

ChannelDrive Bureau
ChannelDrive Bureauhttp://www.channeldrive.in
ChannelDrive Bureau covers the latest developments in the space of ICT, technology, solutions and implementations and delivers content focused around solution providers, system integrators, distributors and technology partner community in India. ChannelDrive Bureau is headed by Zia Askari. He can be reached at ziaaskari@channeldrive.in

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