Intel has integrated its 1.6 Tbps silicon photonics engine with its 12.8 Tbps programmable Ethernet switch.
This co-packaged solution brings together the essential technology building blocks from Intel and its Barefoot Networks Division for integrated optics on an Ethernet switch.
“Our co-packaged optics demonstration is the first step to making optical I/O with silicon photonics a reality. We share the industry belief that co-packaged optics offers power and density advantages for switches at 25 Tbps and higher, and ultimately is a necessary and enabling technology for bandwidth scalability in future networks. The timing of this demonstration shows the technology is ready to support our customers’ requirements,” said, Hong Hou, Intel corporate vice president and general manager of the Silicon Photonics Products Division.
Who It Helps: The co-packaged switch is optimized for hyperscale data centers, where demand for cost-effective interconnect and bandwidth is limitless. Intel is currently demonstrating this technology to customers.
Why It Matters: Today’s data center switches depend on pluggable optics installed in the switch faceplate that are connected to switch serializer/deserializer (SerDes) ports using an electrical trace. But as data center switch bandwidth grows, connecting the SerDes to pluggable optics electrically will be more complex and require more power.
With co-packaged optics, the optical port is placed near the switch within the same package, thus reducing power and enabling continued switch bandwidth scalability.
What is Being Demonstrated: This demonstration brings together the best of Barefoot Networks’ programmable Ethernet switch technology and Intel’s silicon photonics technology. The integrated switch package in this demonstration uses a P4-programmable Barefoot Tofino™ 2 switch ASIC co-packaged with 1.6 Tbps silicon photonics engines from Intel’s Silicon Photonics Product Division.
Barefoot Tofino 2 is a P4-programmable Ethernet switch that delivers up to 12.8 Tbps throughput and is based on the company’s Protocol Independent Switch Architecture (PISA). PISA is programmed using the open source P4 programming language for data planes.
With the P4 data plane, Tofino switches’ forwarding capability can be adapted via software to new needs in the network or to new protocols that are supported by P4. The performance and programmability of Tofino 2 are designed to meet the needs of hyperscale data centers and cloud and service provider networks.
For co-packaged optics, the Barefoot Tofino 2 switch ships in a multi-die package that makes it easier to co-package the optical engine and to upgrade the SerDes for lower power or higher throughput.
“As switch chips scale to meet requirements for demand of limitless bandwidth in cloud-scale data centers, the need for power- and cost-effective interconnect is critical,” said Ed Doe, vice president and general manager of the Barefoot Division. “We have designed our Tofino 2 switch series using leading edge multi-die technology that enables interface flexibility, making it easier for us to integrate and create a scalable co-packaged solution with our silicon photonics products. This has empowered us to deliver an industry-first solution that will greatly advance the future of data center infrastructure and architectures.”
